How do you interface an external MUX IO (eg 3rd party CAN chip) device to the SH1 & SH2 ?
The basic number of cycles for a MUX IO access on SH1& 2 is as follows:SH1 2 cycles address + 2 cycles data. SH2 4 cycles address + 2 cycles data. As this can be too fast for some peripheral chips when the SH is running at 20Mhz +, it is often necessary to add wait states particularly to the data portion of the access. The SH1 does NOT support programmable wait state insertion whereae the SH2 does. Both devices however do support wait state insertion via the WAIT pin. This means the SH2 should normally support a glueless interface to MUX IO devices whereas the SH1 will require some glue logic. This glue logic performs the task of holding the WAIT pin for an extra cycle to extend the data access.