Skip to main content
Knowledgebase
Home
Renesas Electronics Europe - Knowledgebase

How do I correctly configure the simple I2C driver on the SCI module?

Latest Updated:09/19/2016

Question:

How do I correctly configure the simple I2C driver on the SCI module?

Answer:

The existing driver for simple I2C on SCI sets the bit SIMR1.IICDL to 0 in the function sci_siic_open_hw_master() in synergy\ssp\src\driver\r_sci_i2c\r_sci_i2c.c:-

/* Set this SCI channel to operate in simple I2C mode */
HW_SCI_SIIC_ModeSet(p_ctrl->info.channel, SCI_SIIC_MODE_I2C);

/* Set SDA Output Delay */
HW_SCI_SIIC_DataOutputDelay (p_ctrl->info.channel, 0);

Whereas the description in the manual states for simple IIC, these bits should be set in range 1 to 31, in section 34.2.21 (SIMR1 register) :

The IICDL[4:0] bits specify an output delay on the SDAn pin relative to the falling edge of the output on the SCLn pin.
The available delay settings range from no delay to 31 cycles, with the clock signal from the on-chip baud rate generator
as the base. The signal obtained by frequency-dividing PCLKA by the divisor set in SMR.CKS[1:0] is supplied as the
clock signal from the on-chip baud rate generator. Set these bits to 00000b unless operation is in simple IIC mode. In
simple IIC mode, set the bits to a value in the range from 00001b to 11111b.

This error causes I2C communication on simple I2C to be unreliable (e.g. touch controller on S7-DK, also, external I2C device connected via PMOD).

From reading the manual, it seems that the bits in SIMR1.IICDL are:

Delay settings from 0 to 31 clocks, representing periods of the corresponding numbers of cycles of the clock signal from the on-chip baud rate generator (derived by frequency-dividing the base clock, PCLKA, by the divisor selected in the CKS[1:0] bits in SMR), NOT the period of the clock output from the after the BRR register.

So, with PCLKA at 120MHz (max frequency on an S7 device for PCLKA), and CKS[1:0] bits in SMR = 0 (PLCKA/1) then it is not possible to set the required 300ns delay (max delay is 31/120MHz = 258ns), so for S7 devices , PCLKA/4 will need to set as the clock source for Simple IIC, so the required of 300ns can be set in the SIMR1.IICDL bits.

After making these changes IIC communication on simple IIC stability is improved.