Skip to main content
Renesas Electronics Europe - Knowledgebase

Do E_INT0, E_INT1 CnIE and IE M_CTRLn need interrupt-enabled setting?

Latest Updated:12/01/2011


I would like to ask a question about how to confirm the completion of a message transmit/receive operation by the FCAN controller of the V850/SF1.
To make an interrupt to INTCTn or INTCRn occur upon completion, is an interrupt-enabled setting required for all of E_INT0 and E_INT1 of CnIE and IE of M_CTRLn ?


An interrupt-enabled setting must be specified for all of the above when generating an interrupt (INTCTn, INTCRn) from the FCAN block.
However, to actually generate an interrupt in the CPU, you also have to clear the masks (such as CANMK3, CANMK2) in the interrupt control registers + (such as CANIC3, CANIC2).

When the CPU enters the interrupt-enabled state, an INTCTn or INTCRn interrupt is generated upon FCAN transmit/receive completion and the CPU transfers control to the interrupt handler.

Suitable Products