When calculating transfer rate, please be careful in regards to the following items:
1) Calculation of Tr and Tf values
The values Tr and Tf in the formula for transfer rate shown in the "User's Manual: Hardware" need to be recalculated using actual measurements of the SCL clock.
Tr is the time from GND until VIH (VCC x 0.7). Tf is the time from the pull-up voltage of the I2C bus to VIL (VCC x 0.3).
Re-measure the above values and substitute them into the formula to calculate the transfer rate.
2) Digital noise filter circuit
The formula for transfer rate shown in the "User's Manual: Hardware" applies when the digital noise filter circuit is disabled.
If the digital noise filter is enabled, a delay equivalent to the number of noise filter stages is added to the low width and high width of the SCL clock.
Therefore, for example, if the number of noise filter stages is four, you need to set the values of the CBRL and ICBRH registers from which four stages' worth of delays have been subtracted.
3) SCL synchronization circuit
When the RIIC receives a signal output by itself, it starts counting only ICBRL/ICBRH values, then changes the SCL. Therefore, a delay occurs for the time required by the SCL to sample the external state.
The analog noise filter delay time of (120ns：reference value) + IICφ1～2 cycle/cycles are required to detect and sample the SCL rising signal.